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LF to 2.7GHz Dual 60dB TruPwr Detector PRELIMINARY TECHNICAL DATA AD8364
FEATURES
RMS Measurement of High Crest-Factor Signals Dual Channel and Difference Outputs ports Integrated accurately scaled Temperature Sensor Wide Dynamic Range 1 dB over 60 dB @2.2 GHz 0.5 dB Temperature-Stable Linear-in-dB Response Low log conformance ripple +5V Operation at 70 mA, -40C to +85C Small footprint 5x5 mm LFCSP Package
FUNCTIONAL BLOCK DIAGRAM
CHPA DECA COMA VPSR ACMB TEMP ACMA CLPA 24 23 22 21 20 19 TEMP VPSA 25 V2I INHA 2 6 INLA 27 PWDN 2 8 COMR 2 9 INLB 3 0 INHB 3 1 16 VSTA 18 17
Channel A
15 OUTA 14 13 FBKA OUTP
TruPwrTM
OUTA OUTB
12 OUTN 11 FBKB 10 OUTB 9 V2I VSTB
Channel B
TruPwrTM
APPLICATIONS
Wireless Infrastructure Power Amplifier Linearization/Control Antenna VSWR Monitor Devices Gain Control and Measurement Transmitter Signal Strength Indication (TSSI) Dual-Channel Wireless Infrastructure Radios
VPSB 3 2 BIAS 1 2 3 4 5 6 7 8
CHPB DECB COMB ADJB ADJA VREF VLVL CLPB
Figure 1. Functional Block Diagram
GENERAL DESCRIPTION
The AD8364 is a true RMS responding dual channel RF power measurement subsystem for the precise measurement and control of signal power. The flexibility of the AD8364 allows communications systems and instrumentation, such as RF power amplifiers and radio transceiver AGC circuits, to be monitored and controlled with ease. Operating on a single 5V supply, each channel is fully specified for operation up to 2.7GHz, over a dynamic range of 60dB. The AD8364 provides accurately scaled, independent, RMS outputs of both RF measurement channels. A useful measurement difference between the two channels is also made available. On chip channel matching makes the RMS difference output extremely stable with temperature and process variations. The device also includes a useful temperature sensor with an accurately scaled voltage proportional to temperature, specified over the device operating temperature range. The AD8364 can be used with input signals having RMS values from 55dBm to +5dBm, Re: 50 and large crest factors with no accuracy degradation. Integrated in the AD8364 are two well-matched AD8362 channels (see AD8362 data sheet for more info). Enhancements include improved temperature performance and reduced log-conformance ripple versus the AD8362. On chip wide bandwidth op-amps are connected to accommodate flexible configurations that support many system solutions. The device can easily be configured to provide three RMS measurements simultaneously. Linear-in-dB RMS measurements are supplied at OUTA and OUTB, with conveniently scaled slope of 50mV/dB. The RMS difference between OUTA and OUTB is available differentially or single-ended at OUTP and OUTN. An optional voltage applied to VLVL provides a common mode reference level to offset OUTP and OUTN above ground. Each channel of the AD8364 can independently be used to control separate gain control feedback loops using VSTA and VSTB. The difference outputs also provide feedback control while providing improved temperature stability through matched channels. Flexibility exists to use either channel as a reference while the other channel is slaved through a feedback loop. RF power amplifier control, VSWR measurements, and transceiver AGC circuits benefit from this feature. In control modes, the opposite polarities of the OUTP and OUTN outputs allow proportional or complementary gain-control functions, eliminating the need for a board-level signinverting amplifier. Feedback pins FBKA and FBKB allow custom loop regulation in special control system applications and log-slope adjust flexibility. When one channel is slaved off the other, controlling the voltage at VLVL will adjust the slaved channel's RMS value, if a power level offset is desired. The AD8364 is supplied in a 32-lead 5x5mm LFCSP package, for the operating temperature of -40oC to +85oC.
Rev. PrC 1/20/2005
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2005 Analog Devices, Inc. All rights reserved.
PRELIMINARY TECHNICAL DATA
AD8364
AD8364-SPECIFICATIONS
Table I.
Parameters OVERALL FUNCTION SIGNAL INPUT INTERFACE Specified Frequency Range DC Common-Mode Voltage SIGNAL OUTPUT INTERFACE Small Signal Bandwidth Slew Rate Settling Time
(VS =VPSA=VPSB=VPSR =5V, TA=25C, Chan AFREQ = Chan BFREQ, VLVL = VREF, VST[A,B] = OUT[A,B], OUT[P,N] = FBK[A,B], differential input via Balun1, CW input f 2.7GHz unless otherwise noted)
Conditions Channel A and Channel B, CW sine wave input INH[A,B] (Pins 26, 31) INL[A,B] (Pins 27, 30) LF 2.5 OUT[A,B] (Pins 15,10) CLPA = CLPB 300pF CLPA = CLPB 300pF 10%-100% response of -45 dBm to 0 dBm modulated pulse, CLPA=CLPB=Open 100%-10% response of 0 dBm to -45 dBm modulated pulse, CLPA=CLPB=Open, TBD TBD TBD TBD TBD MHz V/S S nS nV/Hz 2.7 GHz V Min Typ Max Units
Wideband Noise MEASUREMENT MODE 450 MHz OPERATION 1 dB Dynamic Range
CLPF = 1000pF, fSPOT 100KHz ADJA = ADJB = 0 V, Error Referred to Best Fit Line using Linear Regression @ PINH[A,B] = -40dBm & -20dBm, TA = 25oC, Balun = M/A-Com MABAES0054 Pins OUT[A,B] -40oC < TA < +85oC
67 65 30 +15 -52 50 -55
dB dB dB dBm dBm mV/dB dBm TBD TBD V V
0.5 dB Dynamic Range Maximum Input Level Minimum Input Level Slope Intercept Output Voltage - High Power In Output Voltage - Low Power In Temperature Sensitivity
-40 C < TA < +85 C 1dB Error 1dB Error
o
o
Pins OUT[A,B] @ PINH[A,B] = -10dBm Pins OUT[A,B] @ PINH[A,B] = -40dBm Deviation from OUT[A,B] @ 25C -40CTBD TBD
2.2 0.7
+/- 0.5 +/- 0.5 +/- 0.5
dB dB dB
+/- 0.3 +/- 0.3 +/- 0.3 TBD TBD TBD
dB dB dB dB dB dB
Deviation from CW Response
5.5dB Peak-to-RMS Ratio (WCDMA 1 Channel) 12dB Peak-to-RMS Ratio (WCDMA 3 Channels) 18dB Peak-to-RMS Ratio (WCDMA 4 Channels)
Rev. PrC Page 2 of 23
PRELIMINARY TECHNICAL DATA
AD8364
AD8364-SPECIFICATIONS
Table I.
Parameters InputA to InputB Isolation InputA to OUTB isolation InputB to OUTA isolation (Note 1) Input Impedance
(VS =VPSA=VPSB=VPSR =5V, TA=25C, Chan AFREQ = Chan BFREQ, VLVL = VREF, VST[A,B] = OUT[A,B], OUT[P,N] = FBK[A,B], differential input via Balun1, CW input f 2.7GHz unless otherwise noted)
Conditions Min Typ 30 PINHB = -50dBm, OUTB = OUTBPINHB 1 dB PINHA = -50dBm, OUTA = OUTAPINHA 1 dB INHA/INLA, INHB/INLB Differential Drive INHA/INLA, INHB/INLB Single-ended Drive 210||0.1 TBD||TBD TBD ||pF ||pF TBD Max Units dB dB
Input Return Loss MEASUREMENT MODE 880MHz OPERATION 1 dB Dynamic Range
With Recommended Balun ADJA = ADJB = 0 V, Error Referred to Best Fit Line using Linear Regression @ PINH[A,B] = -40dBm & -20dBm, TA = 25oC, Balun = M/A-Com ETC 1.6-4-2-3 Pins OUT[A,B] -40 C < TA < +85 C
o o o o
59 54 49 -2 -61 50 -61
dB dB dB dBm dBm mV/dB dBm TBD TBD V V
0.5 dB Dynamic Range Maximum Input Level Minimum Input Level Slope Intercept Output Voltage - High Power In Output Voltage - Low Power In Temperature Sensitivity
-40 C < TA < +85 C 1dB Error 1dB Error
Pins OUT[A,B] @ PINH[A,B] = -10dBm Pins OUT[A,B] @ PINH[A,B] = -40dBm Deviation from OUT[A,B] @ 25C -40CTBD TBD
2.75 1.1
+/- 0.5 +/- 0.5 +/- 0.5
dB dB dB
+/- 0.3 +/- 0.3 +/- 0.3 0.2 0.3 0.3
dB dB dB dB dB dB dB
Deviation from CW Response
5.5dB Peak-to-RMS Ratio (WCDMA 1 Channel) 12dB Peak-to-RMS Ratio (WCDMA 3 Channels) 18dB Peak-to-RMS Ratio (WCDMA 4 Channels)
InputA to InputB Isolation InputA to OUTB isolation InputB to OUTA isolation (Note 1) Input Impedance PINHB = -50dBm, OUTB = OUTBPINHB 1 dB PINHA = -50dBm, OUTA = OUTAPINHA 1 dB INHA/INLA, INHB/INLB Differential Drive INHA/INLA, INHB/INLB Single-ended Drive Input Return Loss With Recommended Balun 200||0.3 TBD||TBD TBD TBD
dB
||pF ||pF
Rev. PrC Page 3 of 23
PRELIMINARY TECHNICAL DATA
AD8364
AD8364-SPECIFICATIONS
Table I.
Parameters MEASUREMENT MODE 1880 MHz OPERATION 1 dB Dynamic Range
(VS =VPSA=VPSB=VPSR =5V, TA=25C, Chan AFREQ = Chan BFREQ, VLVL = VREF, VST[A,B] = OUT[A,B], OUT[P,N] = FBK[A,B], differential input via Balun1, CW input f 2.7GHz unless otherwise noted)
Conditions ADJA = ADJB = 0.75 V, Error Referred to Best Fit Line using Linear Regression @ PINH[A,B] = -40dBm & -20dBm, TA = 25oC, Balun = M/A-Com ETC 1.6-4-2-3 Pins OUT[A,B] -40 C < TA < +85 C
o o o o
Min
Typ
Max
Units
57 52 49 -5 -62 50 -62
dB dB dB dBm dBm mV/dB dBm TBD TBD V V
0.5 dB Dynamic Range Maximum Input Level Minimum Input Level Slope Intercept Output Voltage - High Power In Output Voltage - Low Power In Temperature Sensitivity
-40 C < TA < +85 C 1dB Error 1dB Error
Pins OUT[A,B] @ PINH[A,B] = -10dBm Pins OUT[A,B] @ PINH[A,B] = -40dBm Deviation from OUT[A,B] @ 25C -40CTBD TBD
2.5 1.0
+/- 0.5 +/- 0.5 +/- 0.5
dB dB dB
+/- 0.3 +/- 0.3 +/- 0.3 TBD TBD TBD
dB dB dB dB dB dB dB
Deviation from CW Response
5.5dB Peak-to-RMS Ratio (WCDMA 1 Channel) 12dB Peak-to-RMS Ratio (WCDMA 3 Channels) 18dB Peak-to-RMS Ratio (WCDMA 4 Channels)
InputA to InputB Isolation InputA to OUTB isolation InputB to OUTA isolation (Note 1) Input Impedance PINHB = -50dBm, OUTB = OUTBPINHB 1 dB PINHA = -50dBm, OUTA = OUTAPINHA 1 dB INHA/INLA, INHB/INLB Differential Drive INHA/INLA, INHB/INLB Single-ended Drive Input Return Loss MEASUREMENT MODE 2.14 GHz OPERATION 1 dB Dynamic Range With Recommended Balun ADJA = ADJB = 1.02 V, Error Referred to Best Fit Line using Linear Regression @ PINH[A,B] = -40dBm & -20dBm, TA = 25oC, Balun = M/A-Com ETC 1.6-4-2-3 Pins OUT[A,B] -40oC < TA < +85oC 0.5 dB Dynamic Range Maximum Input Level Minimum Input Level -40 C < TA < +85 C 1dB Error 1dB Error
o o
dB TBD 167||0.14 TBD||TBD TBD ||pF ||pF
56 51 45 -2 -58
dB dB dB dBm dBm
Rev. PrC Page 4 of 23
PRELIMINARY TECHNICAL DATA
AD8364
AD8364-SPECIFICATIONS
Table I.
Parameters Slope Intercept Output Voltage - High Power In Output Voltage - Low Power In Temperature Sensitivity
(VS =VPSA=VPSB=VPSR =5V, TA=25C, Chan AFREQ = Chan BFREQ, VLVL = VREF, VST[A,B] = OUT[A,B], OUT[P,N] = FBK[A,B], differential input via Balun1, CW input f 2.7GHz unless otherwise noted)
Conditions Min Typ 50 -58 Pins OUT[A,B] @ PINH[A,B] = -10dBm Pins OUT[A,B] @ PINH[A,B] = -40dBm Deviation from OUT[A,B] @ 25C -40CDeviation from CW Response
5.5dB Peak-to-RMS Ratio (WCDMA 1 Channel) 12dB Peak-to-RMS Ratio (WCDMA 3 Channels) 18dB Peak-to-RMS Ratio (WCDMA 4 Channels)
InputA to InputB Isolation InputA to OUTB isolation InputB to OUTA isolation (Note 1) Input Impedance
Input Return Loss MEASUREMENT MODE 2.5 GHz OPERATION 1 dB Dynamic Range
With Recommended Balun ADJA = ADJB = 1.14 V, Error Referred to Best Fit Line using Linear Regression @ PINH[A,B] = -40dBm & -20dBm, TA = 25oC, Balun = M/A-Com ETC 1.6-4-2-3 Pins OUT[A,B] -40 C < TA < +85 C
o o o o
58 52 42 5 -53 50 -53
dB dB dB dBm dBm mV/dB dBm TBD TBD V V
0.5 dB Dynamic Range Maximum Input Level Minimum Input Level Slope Intercept Output Voltage - High Power In Output Voltage - Low Power In
-40 C < TA < +85 C 1dB Error 1dB Error
Pins OUT[A,B] @ PINH[A,B] = -10dBm Pins OUT[A,B] @ PINH[A,B] = -40dBm
TBD TBD
2.1 0.65
Rev. PrC Page 5 of 23
PRELIMINARY TECHNICAL DATA
AD8364
AD8364-SPECIFICATIONS
Table I.
Parameters Temperature Sensitivity
(VS =VPSA=VPSB=VPSR =5V, TA=25C, Chan AFREQ = Chan BFREQ, VLVL = VREF, VST[A,B] = OUT[A,B], OUT[P,N] = FBK[A,B], differential input via Balun1, CW input f 2.7GHz unless otherwise noted)
Conditions Deviation from OUT[A,B] @ 25C -40CDeviation from CW Response
5.5dB Peak-to-RMS Ratio (WCDMA 1 Channel) 12dB Peak-to-RMS Ratio (WCDMA 3 Channels) 18dB Peak-to-RMS Ratio (WCDMA 4 Channels)
InputA to InputB Isolation InputA to OUTB isolation InputB to OUTA isolation (Note 1) Input Impedance
Input Return Loss MEASUREMENT MODE 2.7 GHz OPERATION 1 dB Dynamic Range
With Recommended Balun ADJA = ADJB = 1.18 V, Error Referred to Best Fit Line using Linear Regression @ PINH[A,B] = -40dBm & -20dBm, TA = 25oC, Balun = M/A-Com ETC 1.6-4-2-3 Pins OUT[A,B] -40oC < TA < +85oC
60 55 45 10 -50 49 -51
dB dB dB dBm dBm mV/dB dBm TBD TBD V V
0.5 dB Dynamic Range Maximum Input Level Minimum Input Level Slope Intercept Output Voltage - High Power In Output Voltage - Low Power In Temperature Sensitivity
-40oC < TA < +85oC 1dB Error 1dB Error
Pins OUT[A,B] @ PINH[A,B] = -10dBm Pins OUT[A,B] @ PINH[A,B] = -40dBm Deviation from OUT[A,B] @ 25C -40CTBD TBD
2.0 0.5
+/- 0.5 +/- 0.5 +/- 0.5
dB dB dB
Rev. PrC Page 6 of 23
PRELIMINARY TECHNICAL DATA
AD8364
AD8364-SPECIFICATIONS
Table I.
Parameters
(VS =VPSA=VPSB=VPSR =5V, TA=25C, Chan AFREQ = Chan BFREQ, VLVL = VREF, VST[A,B] = OUT[A,B], OUT[P,N] = FBK[A,B], differential input via Balun1, CW input f 2.7GHz unless otherwise noted)
Conditions Deviation from OUT[P,N] @ 25C -40CDeviation from CW Response
5.5dB Peak-to-RMS Ratio (WCDMA 1 Channel) 12dB Peak-to-RMS Ratio (WCDMA 3 Channels) 18dB Peak-to-RMS Ratio (WCDMA 4 Channels)
InputA to InputB Isolation InputA to OUTB isolation InputB to OUTA isolation (Note 1) Input Impedance
Input Return Loss OUTPUT INTERFACE Voltage Range Min Voltage Range Max Source/Sink Current SET-POINT INPUT Voltage Range Input Resistance Logarithmic Scale Factor Logarithmic Intercept Temperature Sensitivity DIFFERENCE OUTPUT Voltage Range Min Voltage Range Max Source/Sink Current Small Signal Bandwidth Slew Rate Wideband Noise Offset
With Recommended Balun Pin OUTA and OUTB RL 200 to ground RL 200 to ground OUTA & OUTB held at VS/2, to 1% change Pin VSTA and VSTB Law conformance error 1dB 0.5
0.09
VS-0.05
V V mA
70
3.75 68
V K mV/dB dBm dB/C
f = 450MHz??, -40C TA +85C f = 450MHz??, -40C TA +85C, Re: 50 Pin = -10dBm, slope and intercept errors combined Pin OUTP and OUTN RL 200 to ground RL 200 to ground OUTP and OUTN held at VS/2, to 1% change CL 300pF CL 300pF CLPF = 1000pF, fSPOT 100KHz OUTB=OUTA=open, OUTP=FBKA=open, VLVL=open
50 -55 TBD
0.1
VS-0.15
V V mA MHz V/S nV/Hz mV
70 TBD TBD TBD TBD
DIFFERENCE LEVEL ADJUST Voltage Range OUT[P,N] Voltage Range Input Resistance
Pin VLVL OUT[P,N]=FBK[A,B} (through Cap) OUT[P,N]=FBK[A,B} (through Cap) 0 0 1
Rev. PrC Page 7 of 23
TBD TBD
V V K
PRELIMINARY TECHNICAL DATA
AD8364
AD8364-SPECIFICATIONS
Table I.
Parameters TEMPERATURE COMPENSATION Input Voltage Range Input Resistance VOLTAGE REFERENCE Output Voltage Temperature Sensitivity Current Limit Source/Sink TEMPERATURE REFERENCE Output Voltage Temperature Slope Current Source/Sink POWER DOWN INTERFACE Logic Level to Enable Logic Level to Disable Input Current
(VS =VPSA=VPSB=VPSR =5V, TA=25C, Chan AFREQ = Chan BFREQ, VLVL = VREF, VST[A,B] = OUT[A,B], OUT[P,N] = FBK[A,B], differential input via Balun1, CW input f 2.7GHz unless otherwise noted)
Conditions Pin ADJA and ADJB 0 <1 Pin VREF RF in = -55 dBm -40C TA +85C Into a grounded load /to 1% change Pin TEMP TA=25C, RL=10K -40C TA +85C, RL=10K TA=25C to 1% change Pin PWDN Logic LO enables Logic HI disables Logic HI PWDN = 5V Logic LO PWDN = 0V 3 100 <1 2 1.6 1 V V A A S S 0.6 2 1.6/2 V mV/C mA 2.5 0.22 18/6 V mV/C mA 2.5 V M Min Typ Max Units
Enable Time Disable Time POWER INTERFACE Supply Voltage Quiescent Current Supply Current Notes (not complete) 1. 2. 3.
PWDN LO to OUTA/OUTB at 100% final value, CLPA/B=Open, CHPA/B=10nF RF in = 0 dBm PWDN HI to OUTA/OUTB at 10% final value, CLPA/B=Open, CHPA/B=10nF, RF in = 0 dBm Pin VPS[A,B], VPSR 4.5 RF in = -55 dBm, Vs =5V PWDN enabled, Vs =5V
5.5 72 500 TBD
V mA A
See Figure/TPC X for a plot of isolation versus frequency for a 1 dB error See Figure/TPC X Best Fit Line, Linear Regression
Rev. PrC Page 8 of 23
PRELIMINARY TECHNICAL DATA
AD8364
ABSOLUTE MAXIMUM RATINGS
Table 2. ADL5306 Absolute Maximum Ratings
Parameter Supply Voltage VPSA, VPSB, VPSR PWDN, VSTA, VSTB, ADJA, ADJB Input power (Re: 50) Internal Power Dissipation JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 sec Rating 5.5V 0V, 5.5V TBD dBm TBDmW TBD C/W +125 C. -40 C to +85 C -65 C to +150 C +300 C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. PrC Page 9 of 23
PRELIMINARY TECHNICAL DATA
AD8364
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
CHPA DECA COMA VPSR ACMB TEMP ACMA CLPA
24
23
22
21
20
19
18
17
TEMP
VPSA
25
16
V2I
VSTA
INHA 2 6 INL A 27 PWD N 2 8 COMR 2 9 INLB 3 0 INHB 3 1 VPSB 3 2
Channel A
15 OUTA
14
TruPwrTM
OUT A OUT B
FBKA OUT P
13
12 OUTN
11
Channel B
FBKB
TruPwrTM
V2I
10 OUTB
9
VSTB
BIAS
1
2
3
4
5
6
7
8
CHPB D ECB COMB ADJB ADJA VR EF VLVL CL PB
Figure 2. AD8364 Pinout
Table 3. Pin Function Descriptions
Pin
1 2,23 3, 22, 29 4, 5
Name
CHPB DECA, DECB COMB, COMA COMR ADJB, ADJA
Description
Connect to common via a capacitor to determine 3 dB point of Channel B input signal high-pass filter. Decoupling terminals for INHA/INLA and INHB/INLB. Connect to common via a large capacitance to complete input circuit. Input system common connection. Connect via low impedance to system common. Temperature compensation for Channel B and Channel A. An external voltage is connected to these pins to improve temperature drift. This voltage can be derived from Vref, that is, connect a resistor from Vref to ADJ[A,B] and another resistor from ADJ[A,B] to ground. The value of these resistors will change with frequency. General-purpose reference voltage output of 2.5V. Reference level input for OUTP and OUTN. (Usually connected to VREF through a voltage divider or left open). Channel B and Channel A connection for loop filter integration (averaging) capacitor. Connect a ground-referenced capacitor to this pin. A resistor can be connected in series with this capacitor to improve loop stability and response time. The voltage applied to this pin sets the decibel value of the required RF input voltage to Channel B that results in zero current out of the loop integrating capacitor pin, CLPB. Channel B output of error amplifier. In measurement mode, normally connected directly to VSTB. Feedback through 1K to the negative terminal of the integrated op-amp driving OUTN. Output of differencing op-amp. In measurement mode, normally connected directly to FBKB. Output of differencing op-amp. In measurement mode, normally connected directly to FBKA. Feedback through 1K to the negative terminal of the integrated op-amp driving OUTP. Channel A output of error amplifier. In measurement mode, normally connected directly to VSTA. The voltage applied to this pin sets the decibel value of the required RF input voltage to Channel A that results in zero current out of the loop integrating capacitor pin, CLPA. Analog common for channel A &B. Connect via low impedance to common. Supply for the input system of channel A & B. Supply for the internal references. Connect to +5 V power supply. Temperature sensor output. Connect to common via a capacitor to determine 3 dB point of Channel A input signal high-pass filter. Channel A "High" and "Low" RF signal input terminal. Disable/Enable control input. Apply logic high voltage to shut AD8364 down. Channel B "Low" and "High" RF signal input terminal. The exposed paddle on the under side of the package should be soldered to a low thermal and electrical impedance ground plane.
Equiv. Circuit
6 7 8, 17
VREF VLVL CLPB, CLPA
9 10 11 12 13 14 15 16 18, 20 21,25,32 19 24 26, 27 28 30, 31 Under Package
VSTB OUTB FBKB OUTN OUTP FBKA OUTA VSTA ACMA, ACMB VPSR, VPSA VPSB TEMP CHPA INHA, INLA PWDN INLB, INHB Exposed Paddle
Circuit A Circuit A
Rev. PrC Page 10 of 23
PRELIMINARY TECHNICAL DATA
AD8364
TYPICAL PERFORMANCE CHARACTERISTICS
VP = 5 V, T = +25C, -40C, +85C; CLPA/B = OPEN. Colors: +25C
Black; -40C
5
Blue; +85C
Red
2.5
5 4.5 4 3.5 3 OUTA (V) 2.5 2 1.5 1 0.5 0 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20
2.5
4.5 2
2
4 1.5
1.5
3.5 1
1 ERROR A (dB) 0.5 0 -0.5 -1 -1.5 -2
0.5 -2 ERROR A (dB) ERROR A (dB) 3 OUTA (V) 0.5
2.5
0
2
-0.5
1.5
-1
1
-1.5
-2.5
0 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 Pin (dBm) -2.5
Pin (dBm)
Figure 3.OUT[A,B] VOUT and Log Conformance vs. Input Amplitude at 450 MHz, Typical Device, TADJA/B = 0V, Sine Wave, Differential Drive
5 2.5
Figure 6. OUT[A,B] VOUT and Log Conformance vs. Input Amplitude at 2.14 GHz, Typical Device, TADJA/B =1.02V , Sine Wave, Differential Drive
5 2.5
4.5
2
4.5
2
4
1.5
4
1.5
3.5
1
3.5
1
ERROR A (dB)
3 OUTA (V)
0.5
3 OUTA (V)
0.5
2.5
0
2.5
0
2
-0.5
2
-0.5
1.5
-1
1.5
-1
1
-1.5
1
-1.5
0.5
-2
0.5
-2
0 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 Pin (dBm)
-2.5
0 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 Pin (dBm)
-2.5
Figure 4. OUT[A,B] VOUT and Log Conformance vs. Input Amplitude at 880 MHz, Typical Device, TADJA/B = 0V, Sine Wave, Differential Drive
5 2.5
Figure 7. OUT[A,B] VOUT and Log Conformance vs. Input Amplitude at 2.5 GHz, Typical Device, TADJA/B =1.14V , Sine Wave, Differential Drive
4.5
2
4
1.5
3.5
1
ERROR A (dB)
3 OUTA (V)
0.5
2.5
0
100 MHz
2
-0.5
1.5
-1
2700 MHz
1 -1.5
0.5
-2
0 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 Pin (dBm)
-2.5
Figure 5. OUT[A,B] VOUT and Log Conformance vs. Input Amplitude at 1.88 GHz, Typical Device, TADJA/B = 0.75V , Sine Wave, Differential Drive
Figure 8. Differential Input Impedance (S11) vs. Frequency; Zo = 50
Rev. PrC Page 11 of 23
PRELIMINARY TECHNICAL DATA
5 5 5 4.5 4 4.5
AD8364
5 4
4
3
4
3
3.5
2
3.5
2
ERROR [P,N] (dB)
2.5
0
2.5
0
2
-1
2
-1
1.5
-2
1.5
-2
1
-3
1
-3
0.5
-4
0.5
-4
0 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 Pin (dBm)
-5
0 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 Pin (dBm)
-5
Figure 9. OUT[P,N] VOUT and Log Conformance vs. Input Amplitude at 450 MHz, With B input held at -25dBM and A input swept, Typical Device, TADJA/B=0V, Sine Wave, Differential Drive
5 5
Figure 12. OUT[P,N] VOUT and Log Conformance vs. Input Amplitude at 2.14 GHz, With B input held at -25dBM and A input swept, Typical Device, TADJA/B=1.02V, Sine Wave, Differential Drive
5 5
4.5
4
4.5
4
4
3
4
3
3.5
2
3.5
2
ERROR [P,N] (dB)
2.5
0
2.5
0
2
-1
2
-1
1.5
-2
1.5
-2
1
-3
1
-3
0.5
-4
0.5
-4
0 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 Pin (dBm)
-5
0 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 Pin (dBm)
-5
Figure 10. OUT[P,N] VOUT and Log Conformance vs. Input Amplitude at 880 MHz, With B input held at -25dBM and A input swept, Typical Device, TADJA/B=0V, Sine Wave, Differential Drive
5 5
Figure 13. OUT[P,N] VOUT and Log Conformance vs. Input Amplitude at 2.5 GHz, With B input held at -25dBM and A input swept, Typical Device, TADJA/B=1.14V, Sine Wave, Differential Drive
2
4.5
4 1.5
4
3 1
3.5
2 0.5 ERROR [P,N] (dB)
3 OUT[P,N] (V)
1
2.5
0
ERROR (dB)
0
2
-1
-0.5 1.5 -2 -1 1 -3 -1.5 0.5 -4
0 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 Pin (dBm)
-5
-2 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 Pin (dBm)
Figure 11. OUT[P,N] VOUT and Log Conformance vs. Input Amplitude at 1.88 GHz, With B input held at -25dBM and A input swept, Typical Device, TADJA/B=0.75V, Sine Wave, Differential Drive
Figure 14. Distribution of OUT[A,B] Error over Temperature after Ambient Normalization vs. Input Amplitude for 10 Devices, Frequency=450 MHz, TADJA/B = 0V, Sine Wave, Differential Drive
Rev. PrC Page 12 of 23
ERROR [P,N] (dB)
3 OUT[P,N] (V)
1
3 OUT[P,N] (V)
1
ERROR [P,N] (dB)
3 OUT[P,N] (V)
1
3 OUT[P,N] (V)
1
PRELIMINARY TECHNICAL DATA
2 2
AD8364
1.5
1.5
1
1
0.5 ERROR (dB) ERROR (dB) -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10
0.5
0
0
-0.5
-0.5
-1
-1
-1.5
-1.5
-2 Pin (dBm)
-2 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 Pin (dBm)
Figure 15. Distribution of OUT[A,B] Error at Temperature after Ambient Normalization vs. Input Amplitude for 10 Devices, Frequency= 880 MHz, TADJA/B = 0V , Sine Wave, Differential Drive
2
Figure 18. Distribution of OUT[A,B] Error at Temperature after Ambient Normalization vs. Input Amplitude for 10 Devices, Frequency=2.5 GHz, TADJA/B = 1.14V , Sine Wave, Differential Drive
2
1.5
1
1 Error (dB)
Phase: INLx wrt INHx
0.5 ERROR (dB)
0
0
-0.5
-1 INHx < INLx -2 -40 -30 -20 -10 RFin (dBm) 0 10 20
Ideal +5 -5 +15 -15 -1dB
-1
-1.5
-2 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 Pin (dBm)
Figure 16. Distribution of OUT[A,B] Error at Temperature after Ambient Normalization vs. Input Amplitude for 10 Devices, Frequency=1.88 GHz, TADJA/B = 0.75V, Sine Wave, Differential Drive
2
Figure 19. VOUT and Log Conformance vs. Input Amplitude for magnitude balance of 0 dB, and -1 dB and phase balance of 0 deg, 5 deg, 15 deg at 450 MHz, Typical Device, TADJA/B = 0V, Sine Wave, Differential Drive
1.5
1
0.5 ERROR (dB)
0
-0.5
-1
-1.5
-2 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 Pin (dBm)
Figure 17. Distribution of OUT[A,B] Error at Temperature after Ambient Normalization vs. Input Amplitude for 10 Devices, Frequency=2.14 GHz, TADJA/B = 1.02V , Sine Wave, Differential Drive
Figure 20. Output Response to RF Burst Input for Various RF Input Levels, Carrier Frequency 450 MHz, CLPA/B = 0
Rev. PrC Page 13 of 23
PRELIMINARY TECHNICAL DATA
14 12
AD8364
TOTAL = 40 DEVICES RF INPUT = -60 dBm
10
Count
8
6
4
2
0 2.486 2.488 2.49 2.492 2.494
Figure 21. Output Response to RF Burst Input for Various RF Input Levels, Carrier Frequency 450 MHz, CLPA/B = 0.1 F
8
VREF (VOLTS)
2.496
2.498
2.5
2.502
2.504
2.506
Figure 24. Distribution of VREF for 40 Devices
7
TOTAL = 40 DEVICES RF INPUT = -60 dBm
6
5
Count
4
3
2
1
0 0.617 0.619 0.621
Figure 22. Output Response Using Power-Down Mode for Various RF Input Levels, Carrier Frequency 450 MHz, CLPA = 0
TEMP (VOLTS)
0.623
0.625
0.627
Figure 25. Distribution of TEMP voltage for 40 Devices
20
15
10
Change in VREF (mV)
5
0
-5
-10
-15
-20 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temp (degC)
Figure 23. Output Response Using Power-Down Mode for Various RF Input Levels, Carrier Frequency 450 MHz, CLPA = 0.1 F, CHPA = 10nF
Figure 26. Change in VREF vs. Temperature, 11 parts
Rev. PrC Page 14 of 23
PRELIMINARY TECHNICAL DATA
4 2
AD8364
3.5
1.5
3
1
CW VOUT 1 CHANNEL VOUT 3 CHANNEL VOUT 4 CHANNEL VOUT 11 CHANNEL VOUT CW ERROR 1 CHANNEL ERROR 3 CHANNEL ERROR 4 CHANNEL ERROR 11 CHANNEL ERROR
2.5 OUTA (Volts)
0.5 ERROR (dB)
2
0
1.5
-0.5
1
-1
0.5
-1.5
0 -60 -55 -50 -45 -40 -35 -30 -25 Pin (dBm) -20 -15 -10 -5 0 5 10
-2
Figure 27. Output Voltage and Error from CW Linear Reference vs. Input Amplitude with Different Waveforms, CW, WCDMA1,3,4 and 11Channel, Frequency 880MHz.
4
2
3.5
1.5
3
1 CW VOUT
2.5 OUTA (Volts)
0.5 ERROR (dB)
2
0
1 CHANNEL VOUT 3 CHANNEL VOUT 4 CHANNEL VOUT CW ERROR 1 CHANNEL ERROR 3 CHANNEL ERROR 4 CHANNEL ERROR
1.5
-0.5
1
-1
0.5
-1.5
0 -60 -55 -50 -45 -40 -35 -30 -25 Pin (dBm) -20 -15 -10 -5 0 5 10
-2
Figure 28. Output Voltage and Error from CW Linear Reference vs. Input Amplitude with Different Waveforms, CW, WCDMA 1,3,4-Channel, Frequency 2140 MHz
Rev. PrC Page 15 of 23
PRELIMINARY TECHNICAL DATA
GENERAL DESCRIPTION AND THEORY
AD8364
Square Law Detector and Amplitude Target The output of the VGA, called VSIG, is applied to a wideband square law detector. The detector provides the true RMS response of the RF input signal, independent of waveform, up to crest factors of 6. The detector output, called ISQU, is a fluctuating current with positive mean value. The difference between ISQU and an internally generated current, ITGT[A,B],is integrated by CF and a capacitor attached to CLP[A,B]. CF is the on chip 25pF filter capacitor. CLP[A,B] can be used to arbitrarily increase the averaging time while trading off response time. When the AGC loop is at equilibrium: MEAN(ISQU) = ITGT[A,B] This equilibrium occurs only when: MEAN(VSIG2) = VTGT[A,B]2 (4) (3)
The AD8364 is a dual channel 2.7GHz true RMS responding detector with 60 dB measurement range and incorporates two AD8362 channels with shared reference circuitry (See the AD8362 datasheet for more information). Multiple enhancements have been made to the AD8362 cores to improve measurement accuracy. Log-conformance peak-to-peak ripple has been reduced to < 0.2 dB, over the entire dynamic range. Temperature stability of the RMS output measurements provides < 0.5 dB error over the specified temperature range of -40oC to 85oC, through proprietary techniques. The use of well matched channels offers extremely temperature stable channel difference outputs at OUTP and OUTN. Given well matched channels through IC integration, the RMS measurement outputs, OUTA and OUTB, will drift in the same manner (< 0.5 dB). With OUTP shorted to FBKA, the function at OUTP is: OUTP = OUTA - OUTB + VLVL When OUTN is shorted to FBKB, the function at OUTN is: OUTN = OUTB - OUTA + VLVL (2) (1)
Where VTGT is an attenuated version of the VREF voltage.
The difference outputs, OUTP and OUTN, are insensitive to the common drift due to the difference cancellation of OUTA and OUTB. The AD8364 is a fully calibrated RMS-to-DC converter capable of operation from signals as low as a few Hertz to at least 2.7GHz. Unlike logarithmic amplifiers, the AD8364 response is waveform independent. The device accurately measures waveforms having a high peak-to-rms ratio (crest factor). A block diagram is shown below in figure 29.
CHPA DECA COMA VPSR ACOM TEMP ACOM CLPA 24 23 22 21 20 19 TEMP VPSA 25 V2I INHA 2 6 INLA 2 7 PWDN 2 8 COMR 2 9 INLB 3 0 INHB 3 1 VPSB 3 2 V2I BIAS 1 2 3 4 5 6 7 8 16 VSTA 18 17
Since the square law detectors are electrically identical and well matched, process and temperature-dependant variations are effectively cancelled.
-28 to +40dB INH[A,B] Matched Wide Band Squarers AmplitudeTarget for VSIG Temperature Compensation
VIN
INL[A,B]
Offset - Nulling
VGA
VSIG GSET
Set-Point Interface
x2
ISQU
x2
VREF ITGT
CF
ADJ[A,B]
CHP[A,B]
VST[A,B]
VST[A,B] CLP[A,B]
Output Buffer
VOUT[A,B]
OUT[A,B]
VREF
VREF
2.5V
Band-Gap Reference
CLPF
external
Internal resistors set buffer gain to 5 ACOM
Figure 30. Single Channel Details
Channel A
15 OUTA 14 FBKA 13 OUTP
TruPwrTM
OUTA OUTB
By forcing the above identity through varying the VGA setpoint, it is apparent that: RMS(VSIG) = (MEAN(VSIG2)) = (VTGT2) = VTGT Substituting the value of VSIG, we have: RMS(G0*RFIN exp(-VST[A,B]/VGNS)) = VTGT (6) When connected as a measurement device VST[A,B] = OUT[A,B]. Solving for OUT[A,B] as a function of RFIN: OUT[A,B] = VSLOPE*Log10(RMS(RFIN)/VZ) (7) Where VSLOPE is approximately1V/decade or 50mV/dB. VZ is the intercept voltage, since Log10(1) = 0 when RMS(RFIN) = VZ. If desired, the effective value of VSLOPE may be altered by (5)
22 OUTN 11 FBKB 10 OUTB 9 VSTB
Channel B
TruPwrTM
CHPB DECB COMB ADJB ADJA VREF VLVL CLPB
Figure 29. Block Diagram
A single channel of the AD8364 consists of a high performance AGC loop. Referring to figure 30, the AGC loop is comprised of a wide bandwidth variable gain amplifier (VGA), square law detectors, Amplitude Target circuit, and output driver. For more
detailed description of the functional blocks, see AD8362 data sheet.
Rev. PrC Page 16 of 23
PRELIMINARY TECHNICAL DATA
using a resistor divider from OUT[A,B] to drive VST[A,B]. The intercept, VZ, is approximately 316V (-70 dBV) with a CW signal. This is the extrapolated intercept since OUT[A,B] does not measure down to 0V. In most applications, the AGC loop is closed through the set point interface, VST[A,B]. In measurement mode, OUT[A,B] is tied to VST[A,B], respectively. In controller mode, a control voltage is applied to VST[A,B]. Pins OUT[A,B] drive the control input of a system. The RF feedback signal to the input pins is forced to have an RMS value determined by VSTA or VSTB. RF Input interface The AD8364's RF inputs are connected as shown in figure 31. There are 100 resistors connected between DEC[A,B] and INH[A,B] and INL[A,B]. The mid-point is wired to a pin called DEC[A,B]. Internally to the IC, the DC level on DEC[A,B] is established as (7*VPS[A,B] + 55*Vbe)/30. With a 5V supply, DEC[A,B] is at about 2.6V. Signal coupling capacitors must be connected from the input signal to the INH[A,B] and INL[A,B] pins. The high-pass corner is found as: fhigh-pass = 1/(2**100*C) (8)
AD8364
(1/(2**5K*25pF)), sufficiently low for most HF applications. The high pass corner can be reduced by a capacitor from CHP[A,B] to ground. The input offset voltage varies depending on the actual gain at which the VGA is operating, and thus, on the input signal amplitude. When an excessively large value of CHP[A,B] is used, the offset correction process may lag the more rapid changes in the VGA's gain, which may increase the time required for the loop to fully settle for a given steady input amplitude. Temperature Sensor Interface The AD8364 provides a temperature sensor output capable of driving about 1.6 mA. A 330 internal resistor is connected from TEMP to COMR to provide current sink capability. The temperature scaling factor of the output voltage is approximately 2mV/oC. The typical absolute voltage at 27oC is about 630 mV. VREF Interface An internal voltage reference is provided to the user at pin VREF. The VREF voltage is a temperature stable 2.5V reference that can drive about 18mA. An 830 internal resistor is connected from VREF to ACOM for 6mA sink capability. Power Down Interface The operating and stand-by currents for the AD8364 at 27C are approximately 72 mA and 500 A respectively; The PWDN pin is connected to an internal resistor divider made with two 42K resistors. The divider voltage is applied to the base of an npn transistor to force a power down condition when the device is active. Typically when PWDN is pulled greater than 1.6V the device is powered down. Figure 22 shows typical response times for various RF input levels. The output reaches to within 0.1 dB of its steady-state value in about 1.6 s; the reference voltage is available to full accuracy in a much shorter time. This "wake-up" response will vary in detail depending on the input coupling means and the capacitances CDEC[A,B], CHP[A,B] and CLP[A,B]; these result are for a measurement system operating in the 0.8 to 2 GHz range, balun-coupled at the input port, with CDEC[A,B] = 100 nF, CHP[A,B] = Open and CLP[A,B] = Open. VST[A,B] Interface The VST[A,B] interface has a high input impedance of 72K. The voltage at VST[A,B] is converted to an internal current used to steer the VGA gain. The VGA attenuation control is set to 20 dB/V.
A decoupling capacitor should be connected from DEC[A,B] to ground to attenuate any signal at the mid-point. A 100pF and 0.1 F cap from DEC[A,B] to ground are recommended with a 1nF coupling capacitor such that signals above 1.6MHz can be measured. For coupling of signals below 1.6MHz, a good rule of thumb would be to use 100*Ccoupling for the DEC[A,B] capacitor.
DEC[A,B]
VPOS
COMM INH[A,B]
VIN
INL[A,B] VPOS VPOS
VGA
COMM
COMM
Figure 31. AD8364 RF Inputs
Offset Compensation An offset-nulling loop is used to address small DC offsets in the VGA. The high-pass corner frequency of this loop is internally preset to about 1 MHz using an on chip capacitor of 25pF
Rev. PrC Page 17 of 23
PRELIMINARY TECHNICAL DATA
OUT[A,B,P,N] Outputs The output drivers used in the AD8364 are different than the output stage on the AD8362. The AD8364 incorporates rail-torail output drivers with pull-up and pull-down capability. OUT[A,B,P,N] can source and sink up 70mA. There is also an internal load from both OUTA and OUTB to ACOM of 2.5K. Measurement Difference Output using OUT[P,N] The AD8364 incorporates two operational amplifiers with railto-rail output capability to provide a difference output. As in the case of the output drivers for OUT[A,B], the output stages have the capability of driving 160mA. OUTA and OUTB are internally connected through 1K resistors to the inputs of each op-amp. The pin VLVL is connected to the positive terminal of both op-amps through 1K resistors to provide level shifting. The negative feedback terminal is also made available through a 1K resistor. The input impedance of VLVL is 1K and FBK[A,B] is 2K.. See figure 32 below for the connections of these pins.
CHPA DECA COMA VPSR ACMB TEMP ACMA CLPA 24 23 22 21 20 19 TEMP VPSA 25 V2I INHA 2 6 INL A 27 PWDN 2 8 COMR 2 9 INLB 3 0 INHB 3 1 VPSB 3 2 V2I BIAS 1 2 3 4 5 6 7 8 16 VSTA 18 17
AD8364
OUTB = (OUTA + VLVL)/2 (11) The output value from OUTN may or may not be useful. It is given by: OUTN = 0V (12) For VLVL < OUTA/3, Else, OUTN = (3*VLVL - OUTA)/2 (13)
Channel A
15 OUTA 14 13 FBKA OUTP
TruPwrTM
OUTA OUTB
12 OUTN 11 FBKB 10 OUTB 9 VSTB
Channel B
If VLVL is connected to OUTA, then OUTB will be forced to equal OUTA through the feedback loop. This flexibility provides the user with the capability to measure one channel operating at given power level and frequency while forcing the other channel to the same power level, or another desired power level, at another frequency. If both channels are operating at the same frequency and ADJA = ADJB, then there will be little to no temperature drift. When different frequencies are driven into each channel, ADJA and ADJB must be set accordingly to reduce the temperature drift of the output measurement. The temperature drift will be a statistical sum of the drift from Channel A and Channel B. As stated before, VLVL can be used to force the slaved channel to operate at a different power than the other channel. If the two channels are forced to operate at different power level, then some static offset will occur due to voltage drops across metal wiring internal to the IC. If an inversion is necessary in the feedback loop, OUTN can be used as the integrator by placing a capacitor between OUTN and OUTP. This changes the output equation for OUTB and OUTP to: OUTB = 2*OUTA - VLVL For VLVL < OUTA/2, (14)
TruPwrTM
CHPB DECB COMB ADJB ADJA VREF VLVL CLPB
Figure 32. Op-Amp Connections (All resistors are 1K12%)
If OUTP is connected to FBKA, then OUTP will be given as: OUTP = OUTA - OUTB + VLVL (9) OUTN = 0V If OUTN is connected to FBKB, then OUTN will be given as: Else, OUTN = OUTB - OUTA + VLVL (10) OUTN = 2*VLVL - OUTA In this configuration, all four measurements are made available simultaneously OUT[A,B,P,N]. A differential output can be taken from OUTP - OUTN and VLVL can be used to adjust the common mode level for an ADC connection. Controller mode The difference outputs can be used for controlling a feedback loop to the AD8364's RF inputs. A capacitor connected between FBKA and OUTP will form an integrator, keeping in mind that the 1K feedback resistor forms a zero. The sheet resistance of the on chip resistors is 12%. If Channel A is driven and Channel B has a feedback loop from OUTP through a PA, then OUTP will integrate to a voltage value such that: (16) The above equations are valid when Channel A is driven and Channel B is slaved through a feedback loop. When Channel B is driven and Channel B is slaved, the above equations can be altered by changing OUTB to OUTA and OUTN to OUTP. Temperature Compensation Adjustment The AD8364 has a highly stable measurement output with respect to temperature. However, when the RF inputs exceed a frequency of 1.7GHz, the output temperature drift must be compensated using ADJ[A/B]. Proprietary techniques are used to compensate for the temperature drift. However, the (15)
Rev. PrC Page 18 of 23
PRELIMINARY TECHNICAL DATA
absolute value of compensation is different for various frequencies. The following chart can be used to apply the appropriate ADJ[A/B] voltage to maintain a temperature drift error less than +/- 0.5dB over the entire temperature range.
F (MHz) ADJ[A/B] (V) 450 0 900 0 1700 0 1900 0.75 Table 4 2200 1.02 2500 1.14 2700 1.18
VPSA 25 V2I INHA 2 6 INLA 27 PW DN 2 8 CO MR 2 9
AD8364
increased to 100 mV/dB. This choice of scaling is useful when the output is applied to a digital voltmeter because the displayed number reads as a decibel quantity directly, with only a decimal point shift.
CHPA DECA COMA VPSR ACMB TEMP ACMA CLPA 24 23 22 21 20 19 TEMP 16 VSTA 18 17
TruPwrTM
OUTA OUTB
Channel A
15 OUTA 14 13 FBKA OUTP
12 OUTN 11 FBKB 10 OUTB 9 V2I
Compensating the device for temperature drift using ADJ[A/B] allows for great flexibility. If the user requires minimum temperature drift at a given input power or subset of the dynamic range, the ADJ[A,B] voltage can be swept while monitoring OUT[A,B] over temperature. Figure 33 shows an example of this. The ADJ[A,B] value where the output does not change is the voltage that must be applied to have minimum temperature drift at the given power and frequency.
1.7
INLB 3 0 INHB 3 1 VPSB 3 2
Channel B
TruPwrTM
Vout R1
VSTB
BIAS 1 2 3 4 5 6 7 8
R2
CHPB DECB COMB ADJB ADJA VREF VLVL CLPB
Figure 34. External Network to Raise Slope
85C
1.65
65C
1.6
45C
OUTA (V)
Operation at high slopes is useful when a particular sub-range of the input is measured in greater detail. However, a measurement range of 60 dB would correspond to a 6 V change in VOUT at this slope, exceeding the capacity of the AD8364's output stage when operating on a 5 V supply. This requires that the intercept is repositioned to place the desired sub-range within a window corresponding to an output range of 0.2 V VOUT 4.8 V, a 46 dB range.
Using the arrangement shown in
CHPA DECA COMA VPSR ACMB T EMP ACMA CLPA 24 23 22 21 20 19 TEMP 18 17
1.55
25C 10C
1.5
-20C
1.45
V PSA
25 V2I
16
VSTA
IN HA 2 6
Channel A
15 OUTA 14 13 FBKA OUTP
-40C
1.4 0 0.25 0.5 0.75 1 1.25 ADJA (V) 1.5 1.75 2 2.25 2.5
INLA 2 7 PW DN 2 8 CO MR 2 9 INLB 3 0 INHB 3 1 VP SB 3 2
TruPwrTM
OUTA OUTB
12 OUTN 11 FBKB 10 OUTB 9 V2I VSTB
Channel B
TruPwrTM
Vout R1 4.02K Ohms R2 4.32K Ohms
Figure 33. OUTA vs. ADJA over Temp. Pin=-30dBm, 1.9GHz
BIAS 1 2 3 4 5 6 7 8
The ADJ[A,B] input has a high input impedance. The input can be conveniently driven from an attenuated value of VREF, using a resistor divider.
CHPB DECB COMB ADJB ADJA VREF VLVL CLPB
R3 2K Ohms
ALTERING THE SLOPE
None of the changes in operating conditions discussed so far affect the logarithmic slope, VSLP, in Equation 9. However, this can readily be altered by controlling the fraction of VOUT that is fed back to the setpoint interface at the VSET pin. When the full signal from VOUT is applied to VSET, the slope assumes its nominal value of 50 mV/dB. It can be increased by including an attenuator between these pins, as shown in Figure 34. Moderately low resistance values should be used to minimize scaling errors due to the 70 k input resistance at the VSET pin. Keep in mind that this resistor string also loads the output, and it eventually reduces the load-driving capabilities if very low values are used. To calculate the resistor values, use
R1 = R2' (SD 50 - 1)
Figure 35, an output of 0.5 V corresponds to the lower end of the desired sub-range, and 4.5 V corresponds to the upper limit with 3 dB of margin at each end of the range, which is nominally 3 mV rms to 300 mV rms, with the intercept at 1.9 mV rms. Note that R2 is connected to VREF rather than ground. R3 is needed to ensure that the AD8364's reference buffer, which can sink only a small current, is correctly loaded. It is apparent that a variable attenuation factor based on this scheme could provide a manual adjustment of the slope, but there are few situations in which this is of value. When the slope is raised by some factor, the loop capacitor, CLPF, should be raised by the same factor to ensure stability and to preserve a chosen averaging time. The slope can be lowered by placing a two-resistor attenuator after the output pin, following standard practice.
(17)
where SD is the desired slope, expressed in mV/dB, and R2' is the value of R2 in parallel with 70 k. For example, using R1 = 1.65 k and R2 = 1.69 k (R2' = 1.649 k), the nominal slope is
Rev. PrC Page 19 of 23
PRELIMINARY TECHNICAL DATA
CHPA DECA COMA VPSR ACMB T EMP ACMA CLPA 24 23 22 21 20 19 TEMP VPSA 25 V2I INHA 2 6 INLA 2 7 PWDN 2 8 COMR 2 9 INLB 3 0 INHB 3 1 VPSB 3 2 V2I BIAS 1 2 3 4 5 6 7 8 16 VSTA 18 17
AD8364
Channel A
15 OUTA 14 13 FBKA OUTP
TruPwrTM
OUTA OUTB
12 OUTN 11 FBKB 10 OUTB 9 VSTB
Channel B
TruPwrTM
Vout R1 4.02K Ohms R2 4.32K Ohms
CHPB DECB COMB ADJB ADJA VREF VLVL CLPB
R3 2K Ohms
Figure 35. Scheme Providing 100 mV/dB Slope for Operation over a 3 mV to 300 mV Input Range
CHOOSING THE RIGHT VALUE FOR CHPF AND CLPF
The AD8364's variable gain amplifier includes an offset cancellation loop, which introduces a high-pass filter effect in its transfer function. The corner frequency, fHP, of this filter must be below that of the lowest input signal in the desired measurement bandwidth frequency to properly measure the amplitude of the input signal. The required value of the external capacitor is given by
CHP[ A, B ] = 200F 2 x x f HP ( f HP in Hz ) (18)
Thus, for operation at frequencies down to 100 kHz, CHP[A,B] should be 318 pF. In the standard connections for the measurement mode, the VST[A,B] pin is tied to OUT[A,B]. For small changes in input amplitude (a few decibels), the time-domain response of this loop is essentially linear with a 3 dB low-pass corner frequency of nominally fLP = 1/(2xxCLP[A,B] x 1.1 k). Internal time delays around this local loop set the minimum recommended value of this capacitor to about 300 pF, making fLP = 482 KHz. For operation at lower signal frequencies, or whenever the averaging time needs to be longer, use
CLP[ A, B ] = 900F 2 x x f LP ( f LP in Hz ) (19)
When the input signal exhibits large crest factors, such as a WCDMA signal, CLP[A,B] must be much larger than might at first seem necessary. This is due to the presence of significant low frequency components in the complex, pseudo-random modulation, which generates fluctuations in the output of the AD8364.
Rev. PrC Page 20 of 23
PRELIMINARY TECHNICAL DATA
AD8364
Table 5 Evaluation Board Configuration Options Component T1, T2 Function/Notes The dynamic range of the AD8364 is directly related to the magnitude and phase balance of the Balun feeding the RF signal to the part. The evaluation board includes M/A-COM MABAES0031 solderd to the board and two unsoldered M/A-COM ETC1.6-4-2-3. The MABAES0031 has good magnitude and phase balance between 10MHz and 500MHz, then slowly degrades above 500MHz. The performance of the evaluation board will be degraded above 500 MHz due to the balun. The M/A-COM ETC1.6-42-3 broadband baluns allows limited dynamic range performance between 500 - 2500 MHz. Better dynamic range can be achieved by using narrow band baluns with better magnitude and phase performance. Supply filtering/decoupling capacitors Supply filtering/decoupling capacitors VREF filtering/decoupling capacitors VLVL filtering/decoupling capacitors Output low-pass filter capacitors Output low-pass filter capacitors, can be activated by removing jumpers R15 and R6 Input bias-point decoupling capacitors Input bias-point decoupling capacitors Input signal coupling capacitors Input high-pass filter capacitor AD8364 Jumpers Capacitors can be installed for controller mode Optional pull-down resistors 100 Resistor to be added when input coupling from a single-ended source (not installed) To be added for use in slope adjustment (not installed) Power-down/enable or external power-down selector Measurement mode/controller mode selector VLVL VREF/External controll selector ADJA VREF/External controll selector ADJB VREF/External controll selector Part Number M/A-COM MABAES0031 Default Value
C11, C13, C21 C10, C12,C20 C19 C18 C15, C17 C14, C16 C23, C24 C1, C8 C2, C3, C4, C5, C6, C7 C9, C22 DUT R4, R5, R6, R9, R12, R15, R17, R19, R21, R24, R23, R10, R11 R2, R13, R16, R18, R20 R1, R3 R14 SW1 SW2, SW3 SW4 SW5 SW6
0.1 F 100 pF 0.1 F tbd 0.1 F 0.1 F 100 pF 0.1 F 0.1 F 0.1 F AD8364XCP 0
10 k/OPEN 100
Rev. PrC Page 21 of 23
PRELIMINARY TECHNICAL DATA
Evaluation Board (10MHz - 500MHz)
VPOS
AD8364
R23 0 C23 100Pf
R24 0 C8 0.1 R5 0 C13 0.1uF C12 100pF
TEMP SENSOR J4
C14 0.1uF R6 0 C15 0.1uF
R4 0
C11 0.1 C10 100p
C9 0.1uF
22 21 20 24 19 18 17 23 CHPA DECA COMAVPSR ACMB TEMP ACMA CLPA
SW2
C5
T2
MABAES0031 C7 INPA 0.1uF 0.1uF J3 R3 C6
1:4
25 VPSA 26 INHA 27 INLA 28 PWDN
VSTA 16 OUTA 15 FBKA 14 OUTP 13
R10 0
R9 0
B A
0.1uF open
SETPOINT VOLTAGE A J5 OUTPUT VOLTAGE A J6 DIFF OUT + J7 DIFF OUT J8 OUTPUT VOLTAGE B J9 SETPOINT VOLTAGE B J10
PWDN A J2 B VPOS
1:4
SW1
R2 10k C4 R1 0.1uF open C3 0.1uF
AD8364ACPZ
29 COMR 30 INLB 31 INHB 32 VPSB
Exposed Paddle
OUTN 12 FBKB 11 OUTB 10 VSTB 9
R13 open
R11 0 R12 0 R14 open SW3
INPB J1
C2 T1 0.1uF MABAES0031
A B
C20 100p R21 0
CHPB DECB COMB ADJB ADJA VREF VLVL CLPB 1 3 4 5 6 7 8 2
C22 0.1uF R19 0 C1 0.1uF C24 SW6 100pF BA R20 open R18 open R17 0 SW5 BA SW4 AB C19 0.1 R16 open
VREF
C17 0.1uF R15 0 C16 0.1uF
C21 0.1
C18 tbd
VPOS TP1 COMM TP2
VREF
ADJB J13
Figure 36. Evaluation Board
ADJA J12
REF LEVEL VOLTAGE J11
Rev. PrC Page 22 of 23
PRELIMINARY TECHNICAL DATA
AD8364
Figure 37. Package
ORDERING GUIDE
Model AD8364XCP AD8364-EVAL Temperature Range -40C to +85C Package Description 32-Lead LFCSP Evaluation Board Package Option
Rev. PrC Page 23 of 23
PR05334-0-1/05(PrC)
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